Accurate VHDL Delay and Power Characterization of CMOS Logic Cells

نویسندگان

  • N. Dumitru
  • R. Nouta
چکیده

This paper presents a model for characterizing delay and power for CMOS logic cells that accounts for input slope and output capacitance loading. A method for deriving the model parameters and VHDL modeling for simple logic gates is presented. The model makes feasible delay and power estimation at VHDL simulation speed, the errors of the model prediction are less than 5% of Spice results.

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تاریخ انتشار 2007